1. Field of the Invention
The present invention relates in general to integrated circuit (IC) testers and in particular to an IC tester having amorphous logic for real-time analysis of acquired test data.
2. Description of Related Art
A typical "per-pin" general purpose integrated circuit (IC) tester includes a set of channels, one for each pin of an IC device under test (DUT). At various times during a test each channel may either send a test signal to a DUT pin or sample a DUT output signal to produce sample data representing the state or magnitude of the DUT output signal. A host computer separately programs each channel to tell it what to do during the test and when to do it. The host computer then sends a START signal concurrently to all channels to tell them to start the test. During the test all channels operate independently, but they each time their test activities with reference to a master clock signal so that test activities at all DUT pins are synchronized.
It is preferable to use a tester that can analyze data acquired by the channels in real time as it is being acquired. In doing so, the tester can immediately halt the test when it determines that a DUT is defective. This frees the tester to test another IC sooner than if the tester had to complete the full test on the DUT before analyzing any of the sample data. In some testers each channel sampling a DUT output signal compares each sample data value it produces to a value that would be expected if the DUT were operating properly. If the sample data value does not match its expected value, the channel signals the host computer that the DUT has failed the test. The host computer can then signal the other channels to halt the test, log the DUT as having failed the test, signal DUT handling equipment to move a next DUT to be tested into position in the tester, and then signal the channels to start a new test. When the DUT passes a test, one of the channels, or some central resource, signals the host computer that the test is complete.
Some tests call for a more complicated analysis of acquired sample data. For example when we test an A/D converter producing a sequence of N-bit digital output words representing the time varying magnitude of an input analog test signal, we may want a host computer to perform a discrete Fourier analysis on the A/D converter output sequence to determine its frequency components. Some special purpose testers can perform complicated data analysis in real time because they have dedicated hardware logic for quickly analyzing the acquired data and have direct paths from each channel for quickly delivering the acquired data to the that dedicated hardware logic in real time. However in a general purpose IC tester there is no central dedicated hardware logic for analyzing the acquired test data. A host computer can be programmed to analyze the acquired data, but a host computer can't acquire and analyze the data in real time, particularly if the data is being generated quickly. A host computer is too slow to perform the analysis in real time. Also the host computer typically communicates with the channels through a single parallel bus, and such a restricted data path would not allow the host to acquire a large amount of test data from the channels in real time. Since the host computer cannot access and analyze the channels' sample data in real time, each channel simply stores its acquired sample data in a local acquisition memory during the test. The host computer then reads and analyzes the data in the channels' acquisition memories when the test is complete.
What is needed is a general purpose IC tester that can obtain test data from the channels as the channels acquire it and which can be programmed to perform real-time analysis on that sample data.